安装好ORCAD9。2的兄弟,进来一下,让大家都来玩玩仿真
强烈要求装好ORCAD9。2的兄弟们把安装方法共享一下,让中国的的设计水平担高一下。
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@老狼
这样行吗?你安装成功了吗?我怎么安装都出错,能不能指点一下?谢谢!
可以啊,不过我的安装文件不是ISO的,我记得在别的帖子上看到你的好像是ISO的完全版。下面的是readme的内容,不知你是否是这样的。是的话,注意文中打了****的那段话。
发信人: highsun ( ), 信区: NewSoftware
标 题: [NS]Cadence_OrCad_9.2_Complete_Suite
发信站: BBS 水木清华站 (Wed Dec 13 09:30:44 2000)
ftp://166.111.174.3/incoming/NewSoft/OrCAD92
这个东西搞电子的同志们还是很用的上的吧,至少
我们系有们选修课就用这个玩艺儿。虽然过不了多
久要被咱们系给扫地出门了,不过也留点纪念的东
西吧 。呜呜~~~
Cadence_OrCad_9.2_Complete_Suite
Supplier : PDX-Team
Cracker : PDX-Team
Packager : PDX-Team
Release Date : 2000/12/05
Protection : dONGLE
Num # Disks : 30 * 5000000
Rating : [**********] 10/10
Requirements : [586] Cpu [+64MB] Ram
[>200MB] Hd-Space
System : [ ] Dos [■] Win 2000
[ ] Win 3.x [ ] Mac
[■] Win 98 [ ] Novell
[■] Win NT [ ] Linux
RELEASE INFO:
~~~~~~~~~~~~~
In its new Orcad? Release 9.2 software, Cadence? PCB Systems Division
(PSD) is shipping updates to key brands, including: Orcad Capture?, CIS,
Layout, and PSpice? products, as well as overall Windows 2000? readiness.
Web updates and the latest enhancements will also be included on a single
CD release. Here are some of the enhancements you'll enjoy:
New FPGA Design Libraries and Design Flow Support
You're enabled for FPGA design. New libraries for all popular FPGAs and
CPLDs are now included with Capture. Design flows are verified and
documented to support Cadence VHDL Desktop and Synplicity Synplify?
products. See the Cadence PSD web site
(http://mainstream.pcb.cadence.com/fpga/fpgastudio.htm) for more
information.
Vendor Place and route system
Actel Designer Series
Altera MAX+Plus II or Quartus
Atmel Atmel Integrated Development System (IDS)
Lattice Semiconductor IspDesignEXPERT
Lucent Technologies ORCA Foundry
Xilinx Alliance, Foundation, or WebFitter
Capture libraries and application notes for Quicklogic?
(www.quicklogic.com) and Triscend? (www.triscend.com) are also available
for download at factory web sites.
Activeparts Plug-in for SpinCircuit.com
Research and download new part data from the Internet. www.SpinCircuit.com
enables you to search and select parts right off the Internet and place
them directly onto your schematic page, without leaving Capture.
standard parts.
Better Control and Editing of Schematic Properties
Control of data is a breeze with Capture's new spreadsheet editor features
and reporting options. Now, you don't need to scroll across columns to
view or edit a property with the new Pivot option. Simply invert object
and property placement to show objects across the top row and properties
down the left-hand column. The ASCII Import/Export property utility for
part and net properties allows you to use external spreadsheets or
database programs to add, modify, or even calculate new properties for
your schematics.
Improvements for PSpice Users
In response to your feedback, we've implemented the top usability requests
for fast and efficient analog circuit capture, including: most recently
used (MRU) pick on menu bar, additional short-cut keys, and a new
Analog/Mixed-Signal project wizard option that enables you to use an
existing project as a template. These new features smooth the
schematic/simulator cycle.
LAYOUT:
Manual Routing and Track Editing
Single entity
Tracks now move correctly with multiple components even if off grid.
Manual route hinting provides control for preferred 135 (45) or 90 degree
angles. Vias now move using the same hinting algorithms Numerous segment
mode copper share improvements allow shared segments and vias to move as
segments. Optimized manual routing to minimize creation of acute and
90-degree angles. Segment mode treats off-grid tracks the same as on-grid
tracks. During manual routing, Layout displays a ratnest line to a
partially routed track if it is closer than any other target pad. Layout
now retains the connectivity data for copper pours and planes while
manually routing. Any angle mode with real time feedback when angles are
orthogonal or 45-degrees. Copy Route now copies based on net intelligence
rather than by net topology. Allows user to copy tracks on repeated
circuitry without having to set up matching connections ahead of time, but
still adheres to netlist and DRC. Includes test points and free vias as
well as tracks. DRC
New "Allow DRC Errors" mode allows intentional component and track editing
errors to be created with DRC markers automatically appearing and
disappearing in real time. DRC options dialog settings persistent between
sessions. Now, you can display DRC errors on invisible layers using dotted
circles Pads, Vias and Padstack Management
New user option permits moving free vias with components globally.
Now you can assign colors to Free Vias.
Improved padstack selection now allows you to select padstacks by Name,
Height/Width, Layer, Shape, or Miscellaneous properties. For instance, you
can easily pick all padstacks with 36 drill and change to 37, or pick all
pad layers with rectangular padstacks of 35 by 70. Added ability to rotate
pads and thermal reliefs. Layout now properly detects blind vias which are
drilled from opposite sides of the board at the same X-Y location. Added
ability to globally change all vias on a net to a different type. Free Via
options dialog settings persistent between sessions. AutoECO
AutoECO now removes only the segments nearest the component pins when
removing or replacing a component during ECO. UNDO
Now you can UNDO Copy Route.
Plus you can UNDO Mincon.
Miscellaneous
Improved overall stability of Layout.
Spreadsheet items are automatically updated when selecting new objects in
design window. Incompletely drawn rotated square pads from Post Process
output, fixed. Selected components deleted when performing Remove
Violation from Board, fixed. Automatic Board Cleanup
You can now select which actions are performed when Automatic Board
Cleanup is activated. Additionally, you can choose to allow Automatic
Board Cleanup to affect locked tracks. Select from: Miter 90-degree corners
Eliminate acute angles
Optimize Vertices
Optimize Shared Tracks
Optimize Shared Vias
Optimize pad exits
You can also eliminate unused padstacks, footprints or nets from the
design using Auto Cleanup Design. GerbTool
GerbTool design file now uses Layout's color assignments and stacks layers
appropriately for IPC-D-356-Netlist Comparison. Interface and Translator
SPECCTRA Autorouter interface
Width by layer and clearance by layer net properties are now passed from
Layout to SPECCTRA. Layout copper areas are now enclosed by route keepouts
when passed to SPECCTRA. Vias embedded within pads are property changed to
make SPECCTRA 34 percent faster at routing. Free via handling improved.
GenCAD interface
Added user control over test probe size and type.
Added user control over part body definition.
Added user control over test pads and test pins.
DXF interface
Generates 2D projection plots of Layout data onto customer specified
layers. Generates drill plots for blind and buried vias.
Added user control over cross-hairs in drill plots.
Microsim? PCBoards translator
All customer-reported bugs have been fixed.
IDF interface
Corrected a keepout translation bug.
Corrected a mirroring/rotation bug.
INSTALL NOTES:
~~~~~~~~~~~~~~
1. unzip
2. use our installer (or unpack manually)
3. run exe
4. when u r asked for serial... use the following:
App Serial
----------------------------------
Capture A
CaptureCIS B
LayoutStd E
LayoutPlus F
LayoutEngEd G
PSpice H
PSpiceAD I
PSpiceADBasics J
PSpiceOptimizer K
For full products u need only B,F,I,K. These includes the other ones.
After that you will asked for a authorization-code.
Write in any number but only 1 line.
******* DO NOT INSTALL DOCUMENT OPTION *******
After the installation run the patcher PDXOrCADcrk.exe in install dir.
SPECIAL NOTES:
~~~~~~~~~~~~~
If you're interested in one (or more :) of the following positions,
join #PARADOX on EFNet and talk to someone from our council.
- Experienced cracker (ISDN or faster connection preferred)
- ISO/VCD siteop (T1 or faster connection required)
- Shell supplier (legal, fast euro shells)
NOTE: we do not need any couriers or prehunters, so don't bother!
if oyu are able to Supply High Quality AUDIO APPs ..and you want als HQ Crac
k┤s
join our channel and msg a OP
TEAM PARADOX
nothing spezial to say...have fun
发信人: highsun ( ), 信区: NewSoftware
标 题: [NS]Cadence_OrCad_9.2_Complete_Suite
发信站: BBS 水木清华站 (Wed Dec 13 09:30:44 2000)
ftp://166.111.174.3/incoming/NewSoft/OrCAD92
这个东西搞电子的同志们还是很用的上的吧,至少
我们系有们选修课就用这个玩艺儿。虽然过不了多
久要被咱们系给扫地出门了,不过也留点纪念的东
西吧 。呜呜~~~
Cadence_OrCad_9.2_Complete_Suite
Supplier : PDX-Team
Cracker : PDX-Team
Packager : PDX-Team
Release Date : 2000/12/05
Protection : dONGLE
Num # Disks : 30 * 5000000
Rating : [**********] 10/10
Requirements : [586] Cpu [+64MB] Ram
[>200MB] Hd-Space
System : [ ] Dos [■] Win 2000
[ ] Win 3.x [ ] Mac
[■] Win 98 [ ] Novell
[■] Win NT [ ] Linux
RELEASE INFO:
~~~~~~~~~~~~~
In its new Orcad? Release 9.2 software, Cadence? PCB Systems Division
(PSD) is shipping updates to key brands, including: Orcad Capture?, CIS,
Layout, and PSpice? products, as well as overall Windows 2000? readiness.
Web updates and the latest enhancements will also be included on a single
CD release. Here are some of the enhancements you'll enjoy:
New FPGA Design Libraries and Design Flow Support
You're enabled for FPGA design. New libraries for all popular FPGAs and
CPLDs are now included with Capture. Design flows are verified and
documented to support Cadence VHDL Desktop and Synplicity Synplify?
products. See the Cadence PSD web site
(http://mainstream.pcb.cadence.com/fpga/fpgastudio.htm) for more
information.
Vendor Place and route system
Actel Designer Series
Altera MAX+Plus II or Quartus
Atmel Atmel Integrated Development System (IDS)
Lattice Semiconductor IspDesignEXPERT
Lucent Technologies ORCA Foundry
Xilinx Alliance, Foundation, or WebFitter
Capture libraries and application notes for Quicklogic?
(www.quicklogic.com) and Triscend? (www.triscend.com) are also available
for download at factory web sites.
Activeparts Plug-in for SpinCircuit.com
Research and download new part data from the Internet. www.SpinCircuit.com
enables you to search and select parts right off the Internet and place
them directly onto your schematic page, without leaving Capture.
standard parts.
Better Control and Editing of Schematic Properties
Control of data is a breeze with Capture's new spreadsheet editor features
and reporting options. Now, you don't need to scroll across columns to
view or edit a property with the new Pivot option. Simply invert object
and property placement to show objects across the top row and properties
down the left-hand column. The ASCII Import/Export property utility for
part and net properties allows you to use external spreadsheets or
database programs to add, modify, or even calculate new properties for
your schematics.
Improvements for PSpice Users
In response to your feedback, we've implemented the top usability requests
for fast and efficient analog circuit capture, including: most recently
used (MRU) pick on menu bar, additional short-cut keys, and a new
Analog/Mixed-Signal project wizard option that enables you to use an
existing project as a template. These new features smooth the
schematic/simulator cycle.
LAYOUT:
Manual Routing and Track Editing
Single entity
Tracks now move correctly with multiple components even if off grid.
Manual route hinting provides control for preferred 135 (45) or 90 degree
angles. Vias now move using the same hinting algorithms Numerous segment
mode copper share improvements allow shared segments and vias to move as
segments. Optimized manual routing to minimize creation of acute and
90-degree angles. Segment mode treats off-grid tracks the same as on-grid
tracks. During manual routing, Layout displays a ratnest line to a
partially routed track if it is closer than any other target pad. Layout
now retains the connectivity data for copper pours and planes while
manually routing. Any angle mode with real time feedback when angles are
orthogonal or 45-degrees. Copy Route now copies based on net intelligence
rather than by net topology. Allows user to copy tracks on repeated
circuitry without having to set up matching connections ahead of time, but
still adheres to netlist and DRC. Includes test points and free vias as
well as tracks. DRC
New "Allow DRC Errors" mode allows intentional component and track editing
errors to be created with DRC markers automatically appearing and
disappearing in real time. DRC options dialog settings persistent between
sessions. Now, you can display DRC errors on invisible layers using dotted
circles Pads, Vias and Padstack Management
New user option permits moving free vias with components globally.
Now you can assign colors to Free Vias.
Improved padstack selection now allows you to select padstacks by Name,
Height/Width, Layer, Shape, or Miscellaneous properties. For instance, you
can easily pick all padstacks with 36 drill and change to 37, or pick all
pad layers with rectangular padstacks of 35 by 70. Added ability to rotate
pads and thermal reliefs. Layout now properly detects blind vias which are
drilled from opposite sides of the board at the same X-Y location. Added
ability to globally change all vias on a net to a different type. Free Via
options dialog settings persistent between sessions. AutoECO
AutoECO now removes only the segments nearest the component pins when
removing or replacing a component during ECO. UNDO
Now you can UNDO Copy Route.
Plus you can UNDO Mincon.
Miscellaneous
Improved overall stability of Layout.
Spreadsheet items are automatically updated when selecting new objects in
design window. Incompletely drawn rotated square pads from Post Process
output, fixed. Selected components deleted when performing Remove
Violation from Board, fixed. Automatic Board Cleanup
You can now select which actions are performed when Automatic Board
Cleanup is activated. Additionally, you can choose to allow Automatic
Board Cleanup to affect locked tracks. Select from: Miter 90-degree corners
Eliminate acute angles
Optimize Vertices
Optimize Shared Tracks
Optimize Shared Vias
Optimize pad exits
You can also eliminate unused padstacks, footprints or nets from the
design using Auto Cleanup Design. GerbTool
GerbTool design file now uses Layout's color assignments and stacks layers
appropriately for IPC-D-356-Netlist Comparison. Interface and Translator
SPECCTRA Autorouter interface
Width by layer and clearance by layer net properties are now passed from
Layout to SPECCTRA. Layout copper areas are now enclosed by route keepouts
when passed to SPECCTRA. Vias embedded within pads are property changed to
make SPECCTRA 34 percent faster at routing. Free via handling improved.
GenCAD interface
Added user control over test probe size and type.
Added user control over part body definition.
Added user control over test pads and test pins.
DXF interface
Generates 2D projection plots of Layout data onto customer specified
layers. Generates drill plots for blind and buried vias.
Added user control over cross-hairs in drill plots.
Microsim? PCBoards translator
All customer-reported bugs have been fixed.
IDF interface
Corrected a keepout translation bug.
Corrected a mirroring/rotation bug.
INSTALL NOTES:
~~~~~~~~~~~~~~
1. unzip
2. use our installer (or unpack manually)
3. run exe
4. when u r asked for serial... use the following:
App Serial
----------------------------------
Capture A
CaptureCIS B
LayoutStd E
LayoutPlus F
LayoutEngEd G
PSpice H
PSpiceAD I
PSpiceADBasics J
PSpiceOptimizer K
For full products u need only B,F,I,K. These includes the other ones.
After that you will asked for a authorization-code.
Write in any number but only 1 line.
******* DO NOT INSTALL DOCUMENT OPTION *******
After the installation run the patcher PDXOrCADcrk.exe in install dir.
SPECIAL NOTES:
~~~~~~~~~~~~~
If you're interested in one (or more :) of the following positions,
join #PARADOX on EFNet and talk to someone from our council.
- Experienced cracker (ISDN or faster connection preferred)
- ISO/VCD siteop (T1 or faster connection required)
- Shell supplier (legal, fast euro shells)
NOTE: we do not need any couriers or prehunters, so don't bother!
if oyu are able to Supply High Quality AUDIO APPs ..and you want als HQ Crac
k┤s
join our channel and msg a OP
TEAM PARADOX
nothing spezial to say...have fun
0
回复
提示
@goldant
可以啊,不过我的安装文件不是ISO的,我记得在别的帖子上看到你的好像是ISO的完全版。下面的是readme的内容,不知你是否是这样的。是的话,注意文中打了****的那段话。发信人:highsun( ),信区:NewSoftware标 题:[NS]Cadence_OrCad_9.2_Complete_Suite发信站:BBS水木清华站(WedDec1309:30:442000) ftp://166.111.174.3/incoming/NewSoft/OrCAD92 这个东西搞电子的同志们还是很用的上的吧,至少我们系有们选修课就用这个玩艺儿。虽然过不了多久要被咱们系给扫地出门了,不过也留点纪念的东西吧。呜呜~~~ Cadence_OrCad_9.2_Complete_SuiteSupplier:PDX-TeamCracker :PDX-TeamPackager:PDX-TeamReleaseDate:2000/12/05Protection :dONGLENum#Disks :30*5000000Rating :[**********]10/10Requirements:[586]Cpu [+64MB]Ram [>200MB]Hd-SpaceSystem :[]Dos [■]Win2000 []Win3.x[]Mac [■]Win98 []Novell [■]WinNT []LinuxRELEASEINFO:~~~~~~~~~~~~~InitsnewOrcad?Release9.2software,Cadence?PCBSystemsDivision(PSD)isshippingupdatestokeybrands,including:OrcadCapture?,CIS,Layout,andPSpice?products,aswellasoverallWindows2000?readiness.WebupdatesandthelatestenhancementswillalsobeincludedonasingleCDrelease.Herearesomeoftheenhancementsyou'llenjoy: NewFPGADesignLibrariesandDesignFlowSupportYou'reenabledforFPGAdesign.NewlibrariesforallpopularFPGAsandCPLDsarenowincludedwithCapture.DesignflowsareverifiedanddocumentedtosupportCadenceVHDLDesktopandSynplicitySynplify?products.SeetheCadencePSDwebsite(http://mainstream.pcb.cadence.com/fpga/fpgastudio.htm)formoreinformation. VendorPlaceandroutesystemActelDesignerSeriesAlteraMAX+PlusIIorQuartusAtmelAtmelIntegratedDevelopmentSystem(IDS)LatticeSemiconductorIspDesignEXPERTLucentTechnologiesORCAFoundryXilinxAlliance,Foundation,orWebFitter CapturelibrariesandapplicationnotesforQuicklogic?(www.quicklogic.com)andTriscend?(www.triscend.com)arealsoavailablefordownloadatfactorywebsites.ActivepartsPlug-inforSpinCircuit.comResearchanddownloadnewpartdatafromtheInternet.www.SpinCircuit.comenablesyoutosearchandselectpartsrightofftheInternetandplacethemdirectlyontoyourschematicpage,withoutleavingCapture.standardparts. BetterControlandEditingofSchematicPropertiesControlofdataisabreezewithCapture'snewspreadsheeteditorfeaturesandreportingoptions.Now,youdon'tneedtoscrollacrosscolumnstovieworeditapropertywiththenewPivotoption.Simplyinvertobjectandpropertyplacementtoshowobjectsacrossthetoprowandpropertiesdowntheleft-handcolumn.TheASCIIImport/Exportpropertyutilityforpartandnetpropertiesallowsyoutouseexternalspreadsheetsordatabaseprogramstoadd,modify,orevencalculatenewpropertiesforyourschematics. ImprovementsforPSpiceUsersInresponsetoyourfeedback,we'veimplementedthetopusabilityrequestsforfastandefficientanalogcircuitcapture,including:mostrecentlyused(MRU)pickonmenubar,additionalshort-cutkeys,andanewAnalog/Mixed-Signalprojectwizardoptionthatenablesyoutouseanexistingprojectasatemplate.Thesenewfeaturessmooththeschematic/simulatorcycle. LAYOUT: ManualRoutingandTrackEditingSingleentityTracksnowmovecorrectlywithmultiplecomponentsevenifoffgrid.Manualroutehintingprovidescontrolforpreferred135(45)or90degreeangles.ViasnowmoveusingthesamehintingalgorithmsNumeroussegmentmodecoppershareimprovementsallowsharedsegmentsandviastomoveassegments.Optimizedmanualroutingtominimizecreationofacuteand90-degreeangles.Segmentmodetreatsoff-gridtracksthesameason-gridtracks.Duringmanualrouting,Layoutdisplaysaratnestlinetoapartiallyroutedtrackifitiscloserthananyothertargetpad.Layoutnowretainstheconnectivitydataforcopperpoursandplaneswhilemanuallyrouting.Anyanglemodewithrealtimefeedbackwhenanglesareorthogonalor45-degrees.CopyRoutenowcopiesbasedonnetintelligenceratherthanbynettopology.Allowsusertocopytracksonrepeatedcircuitrywithouthavingtosetupmatchingconnectionsaheadoftime,butstilladherestonetlistandDRC.Includestestpointsandfreeviasaswellastracks.DRC New"AllowDRCErrors"modeallowsintentionalcomponentandtrackeditingerrorstobecreatedwithDRCmarkersautomaticallyappearinganddisappearinginrealtime.DRCoptionsdialogsettingspersistentbetweensessions.Now,youcandisplayDRCerrorsoninvisiblelayersusingdottedcirclesPads,ViasandPadstackManagement Newuseroptionpermitsmovingfreeviaswithcomponentsglobally.NowyoucanassigncolorstoFreeVias.ImprovedpadstackselectionnowallowsyoutoselectpadstacksbyName,Height/Width,Layer,Shape,orMiscellaneousproperties.Forinstance,youcaneasilypickallpadstackswith36drillandchangeto37,orpickallpadlayerswithrectangularpadstacksof35by70.Addedabilitytorotatepadsandthermalreliefs.LayoutnowproperlydetectsblindviaswhicharedrilledfromoppositesidesoftheboardatthesameX-Ylocation.Addedabilitytogloballychangeallviasonanettoadifferenttype.FreeViaoptionsdialogsettingspersistentbetweensessions.AutoECOAutoECOnowremovesonlythesegmentsnearestthecomponentpinswhenremovingorreplacingacomponentduringECO.UNDONowyoucanUNDOCopyRoute.PlusyoucanUNDOMincon.Miscellaneous ImprovedoverallstabilityofLayout.Spreadsheetitemsareautomaticallyupdatedwhenselectingnewobjectsindesignwindow.IncompletelydrawnrotatedsquarepadsfromPostProcessoutput,fixed.SelectedcomponentsdeletedwhenperformingRemoveViolationfromBoard,fixed.AutomaticBoardCleanupYoucannowselectwhichactionsareperformedwhenAutomaticBoardCleanupisactivated.Additionally,youcanchoosetoallowAutomaticBoardCleanuptoaffectlockedtracks.Selectfrom:Miter90-degreecornersEliminateacuteanglesOptimizeVerticesOptimizeSharedTracksOptimizeSharedViasOptimizepadexitsYoucanalsoeliminateunusedpadstacks,footprintsornetsfromthedesignusingAutoCleanupDesign.GerbToolGerbTooldesignfilenowusesLayout'scolorassignmentsandstackslayersappropriatelyforIPC-D-356-NetlistComparison.InterfaceandTranslatorSPECCTRAAutorouterinterfaceWidthbylayerandclearancebylayernetpropertiesarenowpassedfromLayouttoSPECCTRA.LayoutcopperareasarenowenclosedbyroutekeepoutswhenpassedtoSPECCTRA.ViasembeddedwithinpadsarepropertychangedtomakeSPECCTRA34percentfasteratrouting.Freeviahandlingimproved. GenCADinterfaceAddedusercontrolovertestprobesizeandtype.Addedusercontroloverpartbodydefinition.Addedusercontrolovertestpadsandtestpins. DXFinterfaceGenerates2DprojectionplotsofLayoutdataontocustomerspecifiedlayers.Generatesdrillplotsforblindandburiedvias.Addedusercontrolovercross-hairsindrillplots.Microsim?PCBoardstranslatorAllcustomer-reportedbugshavebeenfixed.IDFinterfaceCorrectedakeepouttranslationbug.Correctedamirroring/rotationbug. INSTALLNOTES:~~~~~~~~~~~~~~1.unzip2.useourinstaller(orunpackmanually)3.runexe4.whenuraskedforserial...usethefollowing: App Serial ---------------------------------- Capture A CaptureCIS B LayoutStd E LayoutPlus F LayoutEngEd G PSpice H PSpiceAD I PSpiceADBasics J PSpiceOptimizer KForfullproductsuneedonlyB,F,I,K.Theseincludestheotherones.Afterthatyouwillaskedforaauthorization-code.Writeinanynumberbutonly1line. ******* DONOTINSTALLDOCUMENTOPTION*******AftertheinstallationrunthepatcherPDXOrCADcrk.exeininstalldir. SPECIALNOTES:~~~~~~~~~~~~~Ifyou'reinterestedinone(ormore:)ofthefollowingpositions,join#PARADOXonEFNetandtalktosomeonefromourcouncil. -Experiencedcracker(ISDNorfasterconnectionpreferred) -ISO/VCDsiteop(T1orfasterconnectionrequired) -Shellsupplier(legal,fasteuroshells)NOTE:wedonotneedanycouriersorprehunters,sodon'tbother!ifoyuareabletoSupplyHighQualityAUDIOAPPs..andyouwantalsHQCrack┤sjoinourchannelandmsgaOP TEAMPARADOXnothingspezialtosay...havefun
我终于明白了
0
回复
提示
@goldant
可以啊,不过我的安装文件不是ISO的,我记得在别的帖子上看到你的好像是ISO的完全版。下面的是readme的内容,不知你是否是这样的。是的话,注意文中打了****的那段话。发信人:highsun( ),信区:NewSoftware标 题:[NS]Cadence_OrCad_9.2_Complete_Suite发信站:BBS水木清华站(WedDec1309:30:442000) ftp://166.111.174.3/incoming/NewSoft/OrCAD92 这个东西搞电子的同志们还是很用的上的吧,至少我们系有们选修课就用这个玩艺儿。虽然过不了多久要被咱们系给扫地出门了,不过也留点纪念的东西吧。呜呜~~~ Cadence_OrCad_9.2_Complete_SuiteSupplier:PDX-TeamCracker :PDX-TeamPackager:PDX-TeamReleaseDate:2000/12/05Protection :dONGLENum#Disks :30*5000000Rating :[**********]10/10Requirements:[586]Cpu [+64MB]Ram [>200MB]Hd-SpaceSystem :[]Dos [■]Win2000 []Win3.x[]Mac [■]Win98 []Novell [■]WinNT []LinuxRELEASEINFO:~~~~~~~~~~~~~InitsnewOrcad?Release9.2software,Cadence?PCBSystemsDivision(PSD)isshippingupdatestokeybrands,including:OrcadCapture?,CIS,Layout,andPSpice?products,aswellasoverallWindows2000?readiness.WebupdatesandthelatestenhancementswillalsobeincludedonasingleCDrelease.Herearesomeoftheenhancementsyou'llenjoy: NewFPGADesignLibrariesandDesignFlowSupportYou'reenabledforFPGAdesign.NewlibrariesforallpopularFPGAsandCPLDsarenowincludedwithCapture.DesignflowsareverifiedanddocumentedtosupportCadenceVHDLDesktopandSynplicitySynplify?products.SeetheCadencePSDwebsite(http://mainstream.pcb.cadence.com/fpga/fpgastudio.htm)formoreinformation. VendorPlaceandroutesystemActelDesignerSeriesAlteraMAX+PlusIIorQuartusAtmelAtmelIntegratedDevelopmentSystem(IDS)LatticeSemiconductorIspDesignEXPERTLucentTechnologiesORCAFoundryXilinxAlliance,Foundation,orWebFitter CapturelibrariesandapplicationnotesforQuicklogic?(www.quicklogic.com)andTriscend?(www.triscend.com)arealsoavailablefordownloadatfactorywebsites.ActivepartsPlug-inforSpinCircuit.comResearchanddownloadnewpartdatafromtheInternet.www.SpinCircuit.comenablesyoutosearchandselectpartsrightofftheInternetandplacethemdirectlyontoyourschematicpage,withoutleavingCapture.standardparts. BetterControlandEditingofSchematicPropertiesControlofdataisabreezewithCapture'snewspreadsheeteditorfeaturesandreportingoptions.Now,youdon'tneedtoscrollacrosscolumnstovieworeditapropertywiththenewPivotoption.Simplyinvertobjectandpropertyplacementtoshowobjectsacrossthetoprowandpropertiesdowntheleft-handcolumn.TheASCIIImport/Exportpropertyutilityforpartandnetpropertiesallowsyoutouseexternalspreadsheetsordatabaseprogramstoadd,modify,orevencalculatenewpropertiesforyourschematics. ImprovementsforPSpiceUsersInresponsetoyourfeedback,we'veimplementedthetopusabilityrequestsforfastandefficientanalogcircuitcapture,including:mostrecentlyused(MRU)pickonmenubar,additionalshort-cutkeys,andanewAnalog/Mixed-Signalprojectwizardoptionthatenablesyoutouseanexistingprojectasatemplate.Thesenewfeaturessmooththeschematic/simulatorcycle. LAYOUT: ManualRoutingandTrackEditingSingleentityTracksnowmovecorrectlywithmultiplecomponentsevenifoffgrid.Manualroutehintingprovidescontrolforpreferred135(45)or90degreeangles.ViasnowmoveusingthesamehintingalgorithmsNumeroussegmentmodecoppershareimprovementsallowsharedsegmentsandviastomoveassegments.Optimizedmanualroutingtominimizecreationofacuteand90-degreeangles.Segmentmodetreatsoff-gridtracksthesameason-gridtracks.Duringmanualrouting,Layoutdisplaysaratnestlinetoapartiallyroutedtrackifitiscloserthananyothertargetpad.Layoutnowretainstheconnectivitydataforcopperpoursandplaneswhilemanuallyrouting.Anyanglemodewithrealtimefeedbackwhenanglesareorthogonalor45-degrees.CopyRoutenowcopiesbasedonnetintelligenceratherthanbynettopology.Allowsusertocopytracksonrepeatedcircuitrywithouthavingtosetupmatchingconnectionsaheadoftime,butstilladherestonetlistandDRC.Includestestpointsandfreeviasaswellastracks.DRC New"AllowDRCErrors"modeallowsintentionalcomponentandtrackeditingerrorstobecreatedwithDRCmarkersautomaticallyappearinganddisappearinginrealtime.DRCoptionsdialogsettingspersistentbetweensessions.Now,youcandisplayDRCerrorsoninvisiblelayersusingdottedcirclesPads,ViasandPadstackManagement Newuseroptionpermitsmovingfreeviaswithcomponentsglobally.NowyoucanassigncolorstoFreeVias.ImprovedpadstackselectionnowallowsyoutoselectpadstacksbyName,Height/Width,Layer,Shape,orMiscellaneousproperties.Forinstance,youcaneasilypickallpadstackswith36drillandchangeto37,orpickallpadlayerswithrectangularpadstacksof35by70.Addedabilitytorotatepadsandthermalreliefs.LayoutnowproperlydetectsblindviaswhicharedrilledfromoppositesidesoftheboardatthesameX-Ylocation.Addedabilitytogloballychangeallviasonanettoadifferenttype.FreeViaoptionsdialogsettingspersistentbetweensessions.AutoECOAutoECOnowremovesonlythesegmentsnearestthecomponentpinswhenremovingorreplacingacomponentduringECO.UNDONowyoucanUNDOCopyRoute.PlusyoucanUNDOMincon.Miscellaneous ImprovedoverallstabilityofLayout.Spreadsheetitemsareautomaticallyupdatedwhenselectingnewobjectsindesignwindow.IncompletelydrawnrotatedsquarepadsfromPostProcessoutput,fixed.SelectedcomponentsdeletedwhenperformingRemoveViolationfromBoard,fixed.AutomaticBoardCleanupYoucannowselectwhichactionsareperformedwhenAutomaticBoardCleanupisactivated.Additionally,youcanchoosetoallowAutomaticBoardCleanuptoaffectlockedtracks.Selectfrom:Miter90-degreecornersEliminateacuteanglesOptimizeVerticesOptimizeSharedTracksOptimizeSharedViasOptimizepadexitsYoucanalsoeliminateunusedpadstacks,footprintsornetsfromthedesignusingAutoCleanupDesign.GerbToolGerbTooldesignfilenowusesLayout'scolorassignmentsandstackslayersappropriatelyforIPC-D-356-NetlistComparison.InterfaceandTranslatorSPECCTRAAutorouterinterfaceWidthbylayerandclearancebylayernetpropertiesarenowpassedfromLayouttoSPECCTRA.LayoutcopperareasarenowenclosedbyroutekeepoutswhenpassedtoSPECCTRA.ViasembeddedwithinpadsarepropertychangedtomakeSPECCTRA34percentfasteratrouting.Freeviahandlingimproved. GenCADinterfaceAddedusercontrolovertestprobesizeandtype.Addedusercontroloverpartbodydefinition.Addedusercontrolovertestpadsandtestpins. DXFinterfaceGenerates2DprojectionplotsofLayoutdataontocustomerspecifiedlayers.Generatesdrillplotsforblindandburiedvias.Addedusercontrolovercross-hairsindrillplots.Microsim?PCBoardstranslatorAllcustomer-reportedbugshavebeenfixed.IDFinterfaceCorrectedakeepouttranslationbug.Correctedamirroring/rotationbug. INSTALLNOTES:~~~~~~~~~~~~~~1.unzip2.useourinstaller(orunpackmanually)3.runexe4.whenuraskedforserial...usethefollowing: App Serial ---------------------------------- Capture A CaptureCIS B LayoutStd E LayoutPlus F LayoutEngEd G PSpice H PSpiceAD I PSpiceADBasics J PSpiceOptimizer KForfullproductsuneedonlyB,F,I,K.Theseincludestheotherones.Afterthatyouwillaskedforaauthorization-code.Writeinanynumberbutonly1line. ******* DONOTINSTALLDOCUMENTOPTION*******AftertheinstallationrunthepatcherPDXOrCADcrk.exeininstalldir. SPECIALNOTES:~~~~~~~~~~~~~Ifyou'reinterestedinone(ormore:)ofthefollowingpositions,join#PARADOXonEFNetandtalktosomeonefromourcouncil. -Experiencedcracker(ISDNorfasterconnectionpreferred) -ISO/VCDsiteop(T1orfasterconnectionrequired) -Shellsupplier(legal,fasteuroshells)NOTE:wedonotneedanycouriersorprehunters,sodon'tbother!ifoyuareabletoSupplyHighQualityAUDIOAPPs..andyouwantalsHQCrack┤sjoinourchannelandmsgaOP TEAMPARADOXnothingspezialtosay...havefun
多谢你!!
但是,我的安装了,不能在 Win XP 下运行啊!!!
怎么解决啊!?????
谢谢了........
但是,我的安装了,不能在 Win XP 下运行啊!!!
怎么解决啊!?????
谢谢了........
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