并串转换的例子

module ptos(clk,ri,gi,bi,ro,go,bo);
output ro,go,bo;
input[7:0] ri,gi,bi;
input clk;
reg ro,go,bo;
reg[7:0] mem1,mem2,mem3;
reg[3:0] i,k;

always @(negedge clk)
begin
if(i==7)
begin
i<=0;
k<=1;
end
else
begin
i<=i+1;
i<=0;
end
end

always @(posedge k)
begin
  mem1<=ri;
  mem2<=gi;
  mem3<=bi;
end
  
always @(posedge clk)
begin
   ro<=mem1[7];
   go<=mem2[7];
   bo<=mem3[7];
    for(i=0;i<=6;i=i+1)
  begin
  mem1[i+1]<=mem1[i];
  mem2[i+1]<=mem2[i];
  mem3[i+1]<=mem3[i];
  end
end
endmodule

错误是多驱动来驱动mem,怎么解决阿?谢谢各位
http://bbs.ednchina.com/ShowTopic.aspx?id=63497