The control loop is set up to limit the loop bandwidth at
high line (230 Vac) to approximately 15 Hz with a minimum
phase margin of 45°.
![](http://u.dianyuan.com/bbs/u/71/2964831227751632.jpg?x-oss-process=image/watermark,g_center,image_YXJ0aWNsZS9wdWJsaWMvd2F0ZXJtYXJrLnBuZz94LW9zcy1wcm9jZXNzPWltYWdlL3Jlc2l6ZSxQXzQwCg,t_20)
2.The voltage error amplifier is constrained by the two
equations. When this amplifier is compensated with a
pole-zero pair, there will be a unity gain pole which will be
cancelled by the zero at frequency fz.
这两段英文该怎么理解