有源钳位的顺向电源设计

I have got the root cause now, to solve this issue should increase the mag current, this causes the efficiency will be very low, only 86% at the full load condition.

Magnetic current must higher than the reflect current so that ZVS can be achievable, it is the basic of active clamp.

it is right, but the increasing mag current will cause the low efficiency.

It should have a balancing point for the best efficiency.

yeah, but the efficiency still keep in 86-89%,so I wanna give up using this topology, so do you have some good ideas for the Sepic topology, I wanna use this to replace the traditional pfc circuit and using the LLC to be the dc-dc module.

the target of efficiency is 90% total.

no condition, no idea!

I am quite sorry about this, the condition as below,

input 90-264vac 47-440Hz
output 12v/8A
with plastic encloser, thickness is 3mm, size is 2"x4"1.5"(WxLxH),it is difficult to transfer the heat through encloser.

I had never design the PFC with sepic topology, the advantage of sepic seems can not help you for the very high efficiency, and LLC is not very suit for wide bulk range, maybe use the two step voltage for PFC and add SR with active clamp can achieve your efficiency requirement.

我曾经做过SEPIC,但不是在PFC里面.效率不高.

you think me wrong, current desian is pfc+ active clamp with sync rectifier, due to the low efficiency of active clamp, total efficiency can't meet the requirement,

and if use tow step pfc circuit, it is difficult to design the active clamp stage.

so, I decide use Sepic to replace the frist stage to provide stable bulk voltage, about 250vdc, and use LLC to achieve the dc-dc stage.

cmg, thank u very much, could you please give some data about the Sepic you have done, circuit is prefered.

You can try to separate the efficiency of PFC and PWM stage and then you can get the way to improve the efficiency.

yeah, if the efficiency of active clamp can't exceed 90 or more, total efficiency still can't meet requirement.

Yes, u a right, but there is one think may need to care, the variation frequency of LLC is not suit for using SR, the efficiency still hard to improve, is it right?

that is the key point why I use the Sepic, I wanna use this special topology to adjust the bulk voltage and set the LLC at the stable frequency,

So, the way to get stable output is to control the duty cycle of Sepic. no need the variable frequency to control.

Good idea, please also consider how to achieve the hold up time if needed.

hi,jacki,

Do you have any good ideas, my current project is very urgent, need your help.

If there is very urgen schedule, new topology is not prefer, it will waste a lot of time.

Sorry no idea to get 90% efficiency at worst case, if you had got 89%, I'll prefer to do the optimization from current topology, active clamp can meet wide range, the main concern is the drive voltage of SR, and if you can solve this issue, the winner is you!

Using low loss material is also the way to improve the efficiency, and optimize the component value also help.

Does the heat make you to design for such high efficiency? or it is customer requirement?

yeah, the heat froces me to get higher efficiency, and the 89% efficiency is only for dc-dc, pfc stage's efficiency is only 93%( working at ccm mode, because there isn't enought space to layout emi filter). so the total efficiency is about 82.7%.

there is a very long distance to the target.

Hard switch and diode can acheave 82% easily, why you only can got such low efficiency?

I don't think so, to get a high efficiency is very difficult, as we know, for ccm pfc, maybe 93% eff is very good, and for dc-dc stage, 89% is also quite high, but the total efficiency equals to 89*93%, so I need to improve the effuciency of dc-dc stage.

ZCS PFC+3842 can get 83% at 90Vac and 12V/8.3A output,so 82% for active clamp seems not reasonable?

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but the zcs pfc needs two steps emi at least, that means need at least two emi chocks, there isn't enought space to layout them, so that is another concern.

路过!学习了.

hi, jacki,

There are two circuits confused me, our current design used active clamp and active pfc, and it's efficiency achieves about 86.4%, but we have got 84.5% eff on our original product used general topology flyback. the difference is current design is output 60W(5v/12A), and previous one is 60W/(12v/5a).

Can you tell me the root cause, and could u please give me some good advice on pfc design,

Regards,

tom

sure the 5V/12A will have more loss with same topology, but you got higher efficiency with active clamp, means you choise the better topology, but the higher efficiency maybe caused by the SR, that you need to clarify.

I think the ZCS PFC should suit for 60W power level design.

I think so, here is a good news for you, now, pfc stage can get 95% efficiency. so total efficiency will be 88%, it is close to our target.

Yet, I need to optimize dc-dc stage, because there are lot of disadvantages I found during prototype stage.

Good news, congratulation!

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